1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit structures and, more particularly, to the formation of connections to substrates or buried layers therein.
2. Description of the Prior Art
In the fabrication of integrated circuits, it is often desirable or necessary to make connections from the front surface (e.g. the surface on which the integrated circuit is developed in successive layers) of the integrated circuit to the substrate or to a buried layer within the integrated circuit. In particular, in bipolar, FET or BICMOS (e.g. including both bipolar transistors and CMOS on a single chip) technologies, the transistors are formed on a lightly doped epitaxial layer grown on a heavily doped substrate. The heavy doping of the substrate or buried layer is done to raise the conductivity of the substrate and the light doping of the epitaxial layer results in a layer which is substantially non-conductive. However, areas or regions (e.g. of a depth less than the thickness of the epitaxial layer) of the epitaxial layer may be made selectively conductive by alteration of doping levels in order to form portions of the transistors in accordance with a particular, respective technology specific to the transistor to be formed.
In the prior art, connections to a substrate or buried layer were typically made by ion implantation in order to raise the impurity concentration profile within the desired area of the connection. However, a connection formed in this manner poses some difficulties. Consider that the layer through which a connection is to be made is likely to have a substantial thickness in comparison with layers which form parts of the transistor. While ion implantation depth may be regulated over a substantial range by control of ion energy, implantation over a range of depths requires implantation over a range of energies and may result in irregular impurity concentration profiles. This provides only a marginal solution for a mechanism for forming a connection to a substrate or buried layer. While the impurity concentration profile may be smoothed somewhat by diffusion during annealing which is also often done to repair damage to the crystal lattice due to implantation, such annealing may be difficult to reconcile with diffusion which may take place in other parts of the transistor structure which may exist at a particular point in a transistor fabrication process. Further, the thickness of the layer or layers through which the connection is to be made may exceed feasible implantation depths in a particular semiconductor structure. Moreover, such impurity implantation requires the formation of a mask which is subject to misregistration, potentially reducing production yield. At least four steps of mask formation, ion implantation, annealing and mask removal are necessary for the formation of such a connection structure, requiring time, limiting manufacturing throughput and contributing significantly to the cost of the integrated circuit device.
Possibly of more importance, however, the connection structure, described above, which is formed by ion implantation has a relatively high resistance. This implies that the area required for substrate or buried layer contact must be fairly large and preferably distributed to avoid developing different voltages in different areas of the substrate or buried layer. Often, in BICMOS technologies, a substrate or buried layer connection will be formed for each group of bipolar and CMOS transistors. In any case, the aggregate "footprint" of the connection must be of sufficient size to displace a plurality of transistors which could otherwise be formed on the chip.
Formation of connections of reduced resistance by metallization does not solve these problems. Also, masks remain necessary for opening an aperture into which metal may be deposited. Metal is also subject to fatigue or other defects due to differential thermal expansion and contraction relative to the semiconductor material employed. Adhesion to lower and overlying layers of semiconductor materials requires additional deposition or reaction steps and is also a major source of potential integrated circuit defects which may reduce production yields.